A previous application by the present Applicant (GB 2482141A) has described a system and method of controlling the execution of tasks in a system with multiple processors or processing elements where computation has to meet hard real-time constraints. This described the use of application modelling, for example using Unified Modelling Language (UML), to describe the design of a wireless physical layer.
In that application an apparatus is described which consists of a sequence processor, i.e. a programmable processor with an instruction set that implements primitives of UML, which can be programmed with code that represents a sequence of operations defined in UML and generates control signals to trigger operations in the various processing elements; and where signals from the processing elements indicating task completion are further used in conjunction with control primitives to control the execution of subsequent tasks. The system also allows the use of time events generated by a system clock to be included as trigger signals so that hard real-time constraints can be applied to the system. An advantage of the apparatus and method described is that task execution in a set of multiple processors can be very effectively controlled; and furthermore that a sequence of tasks defined in UML can be automatically compiled to microcode to control the operation of the Sequence Processor.
Thus, a modelling tool generates code from the model which targets a dedicated hardware sequence processor. This hardware sequence processor ensures that tasks executing on processors (and indeed tasks/functions running on dedicated hardware blocks) meet their deadlines and their control and data dependencies.
In a multiprocessor system, access to memory is complex because many processing elements can access the memory at various times. If the memory is also frequently recycled (to minimise size), the debugging and verification of the system is extremely difficult.
In addition, in a modern able to support multiple air interface modes such as is needed in future cellular handsets where modes may be defined in software loaded and updated in the field, there may be unexpected interactions in the way the software accesses memory which will cause operational failures from which the system must recover automatically.
Thus it is desirable to have a system that can identify and manage problems in the access of memory in a multiprocessor system, either during the development/debug phase or in normal operation.